ARMv9 Permission Overlay Extension (POE / S1POE) Architecture
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1. Unlocked Vault (Exposed)
2. In-Register 1-Cycle Lockdown
3. Exploit Exfiltration Trapped
4. Memory Tampering Trapped
5. Authorized Fast Access
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Step
Reset
Execution Thread
Op: LDR [VaultAddr]
Actor: Untrusted Module
Page Table Entry (PTE)
Assigned Protection Key:
PKEY = 1
POR_EL0 Register
Key 0: RW (0x3) [Default]
Key 1: RW (0x3) [Vault]
HARDWARE OVERLAY FAULT
SIGSEGV (SEGV_PKUERR)
Protected Vault
Domain: Key 1
AES-256 Private Key
0xCAFEBABE...
EXPOSED
Step: 0 / 4
Select an ARMv9 POE scenario above to observe zero-syscall memory compartmentalization.
Security Insight: ARMv9 POE decouples memory domain permissions from Page Tables into the POR_EL0 CPU register.